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revisions ltr description date (yr-mo-da) approved a changes in accordance with nor 5962-r 114-92. glg 92-01-22 michael a. frye b changes in accordance with nor 5962- r160-98. glg 98-08-06 raymond monnin c boilerplate update and part of five year review. tcr 07-04-13 robert m. heber the original first page of this drawing has been replaced. rev sheet rev c c c c c c c c c c c c c c c c c c c c sheet 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 rev status rev c c c c c c c c c c c c c c of sheets sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 pmic n/a prepared by kenneth rice defense supply center columbus standard microcircuit drawing checked by charles reusing columbus, ohio 43218-3990 http://www.d scc.dla.mil this drawing is available for use by all departments approved by michael a. frye microcircuit, memory, digital, cmos 64k x 8 electrically erasable programmable read only memory (eeprom), monolithic silicon and agencies of the department of defense drawing approval date 91-10-18 amsc n/a revision level c size a cage code 67268 5962-90869 sheet 1 of 34 dscc form 2233 apr 97 5962-e079-07
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 2 dscc form 2234 apr 97 1. scope 1.1 scope . this drawing documents two product assurance class leve ls consisting of high reliability (device classes q and m) and space application (device class v). a c hoice of case outlines and lead finishes ar e available and are reflected in the par t or identifying number (pin). when available, a choice of radiation hardness assu rance (rha) levels are reflected in the pin. 1.2 pin . the pin is as shown in the following example: 5962 - 90869 01 m x a federal stock class designator rha designator (see 1.2.1) device type (see 1.2.2) device class designator case outline (see 1.2.4) lead finish (see 1.2.5) \ / (see 1.2.3) \/ drawing number 1.2.1 rha designator . device classes q and v rha marked devices m eet the mil-prf-38535 specif ied rha levels and are marked with the appropriate rha designator. device cl ass m rha marked devices m eet the mil-prf-38535, appendix a specified rha levels and are marked with the appropriate rha designator. a dash (-) indicates a non-rha device. 1.2.2 device type(s) . the device type(s) identify the circuit function as follows: device type generic number circuit function access time write speed write mode endurance 01 28c512 64k x 8 eeprom 250 ns 10 ms byte/page 10,000 cycle 02 " 64k x 8 eeprom 250 ns 5 ms byte/page 10,000 cycle 03 " 64k x 8 eeprom 200 ns 10 ms byte/page 10,000 cycle 04 " 64k x 8 eeprom 200 ns 5 ms byte/page 10,000 cycle 05 " 64k x 8 eeprom 150 ns 10 ms byte/page 10,000 cycle 06 " 64k x 8 eeprom 150 ns 5 ms byte/page 10,000 cycle 07 " 64k x 8 eeprom 120 ns 10 ms byte/page 10,000 cycle 08 " 64k x 8 eeprom 120 ns 5 ms byte/page 10,000 cycle 09 28c513 64k x 8 eeprom 250 ns 10 ms byte/page 10,000 cycle 10 " 64k x 8 eeprom 250 ns 5 ms byte/page 10,000 cycle 11 " 64k x 8 eeprom 200 ns 10 ms byte/page 10,000 cycle 12 " 64k x 8 eeprom 200 ns 5 ms byte/page 10,000 cycle 13 " 64k x 8 eeprom 150 ns 10 ms byte/page 10,000 cycle 14 " 64k x 8 eeprom 150 ns 5 ms byte/page 10,000 cycle 15 " 64k x 8 eeprom 120 ns 10 ms byte/page 10,000 cycle 16 " 64k x 8 eeprom 120 ns 5 ms byte/page 10,000 cycle 1.2.3 device class designator . the device class designator is a single le tter identifying the product assurance level as follows: device class device requirements documentation m vendor self-certification to the requirements for mil-std-883 compliant, non- jan class level b microcircuits in accordance with mil-prf-38535, appendix a q or v certification and qua lification to mil-prf-38535
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 3 dscc form 2234 apr 97 1.2.4 case outline(s) . the case outline(s) are as des ignated in mil-std-1835 and as follows: outline letter descriptive designator terminals package style x see figure 1 (1.685" x .600" x .225") 32 dual in-line package y c-12 (.560" x .458" x . 120") 32 rectangular chip carrier package z see figure 1 (.830" x .416" x .120") 32 flat package u see figure 1 (.760" x .760" x .120" 36 pin grid array 1.2.5 lead finish . the lead finish is as specified in mil-pr f-38535 for device classes q and v or mil-prf-38535, appendix a for device class m. 1.3 absolute maximum ratings . 1 / 2 / supply voltage range (v cc ) ............................................................................... -0.5 v dc to +6.0 v dc 3 / operating case te mperature range .................................................................... -55 c to +125 c storage temper ature r ange ................................................................................. -65 c to +150 c lead temperature (solder ing, 10 sec onds) ......................................................... +300 c thermal resistance, junction-to-case ( jc ): case x .............................................................................................................. 28 c/w 4 / case y ........................................................................................................... see m il-std-1835 case z ........................................................................................................... 22 c/w 4 / case u ........................................................................................................... 20 c/w 4 / maximum power dissipation (p d ) ...................................................................... 1. 0 watts junction temperature (t j ) ................................................................................ +175 c 5 / enduranc e........................................................................................................... 10, 000 cy cles/byte (minimum) data retent ion ..................................................................................................... 10 years m inimum 1.4 recommended operating conditions . supply voltage range (v cc ) ............................................................................. 4.5 v dc minimum to 5.5 v dc maximum supply voltage (v ss ) ........................................................................................ 0. 0 v dc high level input voltage range (v ih ) .................................................................. 2.0 v dc to v cc + 1.0 v dc low level input voltage range (v il ) ..................................................................... -0.1 v dc to 0.8 v dc case operating temperature range (t c ) ............................................................. -55 c to +125 c 2. applicable documents 2.1 government specif ication, standards, and handbooks . the following specification, standards, and handbooks form a part of this drawing to the extent specif ied herein. unless otherwise specified, t he issues of these doc uments are those cited in the solicitation or contract. department of defense specification mil-prf-38535 - integrated circuits, manufacturing, general specification for. _______ 1 / stresses above the absolute maximum rating may cause permanent damage to the device. extended operation at the maximum levels may degrade performance and affect reliability. 2 / all voltages referenced to v ss (v ss = ground), unless otherwise specified. 3 / negative undershoots to a minimum of -1.0 v are allowed with a maximum of 20 ns pulse width. 4 / when the thermal resistance for this case is s pecified in mil-std-1835, t hat value shall supersede the value indicated herein. 5 / maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of mil-std-883.
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 4 dscc form 2234 apr 97 department of defense standards mil-std-883 - test me thod standard microcircuits. mil-std-1835 - interface standard electronic component case outlines. department of defense handbooks mil-hdbk-103 - list of st andard microcircuit drawings. mil-hdbk-780 - standard microcircuit drawings. (copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the standardization document order desk, 700 robbins avenue, building 4d, philadelphia, pa 19111-5094.) 2.2 non-government publications . the following documents form a part of this document to the extent specified herein. unless otherwise specified, the issues of the documents are the i ssues of the documents cit ed in the solicitation. american society for testing and materials (astm) astm standard f1192 - standard guide for the measurement of single event phenomena (sep) induced by heavy i on irradiation of semiconductor devices. (applications for copies of astm publications should be addressed to: astm international, po box c700, 100 barr harbor drive, west conshohocken, pa 19428-2959; http://www.astm.org .) electronics industries alliance (eia) jedec standard eia/jesd 78 - ic latch-up test. (applications for copies should be addre ssed to the electronics industries allianc e, 2500 wilson boulevard, arlington, va 22201; http://www.j edec.org .) (non-government standards and other publicat ions are normally available from the organizations that pr epare or distribute the documents. these documents also ma y be available in or through libraries or other informational services.) 2.3 order of precedence . in the event of a conflict between the text of this drawing and the refe rences cited herei n, the text of this drawing takes precedence. nothing in this documen t, however, supersedes applicable laws and regulations unless a specific exempti on has been obtained. 3. requirements 3.1 item requirements . the individual item requirements for device classes q and v shall be in accordance with mil-prf-38535 and as specified herein or as modified in the device manufacture r's quality management (qm) plan. the modification in the qm plan shall not affe ct the form, fit, or function as described herein. the individual item requirements for device class m shall be in accordance with mil-prf-38535, appendix a for non-jan class level b devices and as specified herein. 3.2 design, construction, and physical dimensions . the design, construction, and physical dimensions shall be as specified in mil-prf-38535 and herein for device classes q and v or mil-prf-38535, appendix a and herein for device class m. 3.2.1 case outlines . the case outline(s) shall be in a ccordance with 1.2.4 herein and figure 1. 3.2.2 terminal connections . the terminal connections shall be as specified on figure 2. 3.2.3 truth table . the truth table shall be as specified on figure 3. 3.2.4 radiation exposure circuit . the radiation exposure circuit shall be as specified in 4.4.5e. 3.3 electrical performance characteri stics and postirradiati on parameter limits . unless otherwise specified herein, the electrical performance characteristics and pos tirradiation parameter limits are as specified in table ia and shall apply over t he full case operating temperature range.
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 5 dscc form 2234 apr 97 3.4 electrical test requirements . the electrical test requirements shall be the subgroups specified in table iia. the electrical tests for each subgroup are defined in table ia. 3.5 marking . the part shall be marked with the pin listed in 1.2 her ein. in addition, the manufacturer's pin may also be marked. for packages where marking of t he entire smd pin number is not feasible due to space lim itations, the manufacturer has the option of not marking the "5962-" on the device. for rha product using this option, the rha designator shall still be marked. marking for device classes q and v shall be in accor dance with mil-prf-38535. marking for device class m shall be in accordance with mil-prf-38535, appendix a. 3.5.1 certificat ion/compliance mark . the certification mark for device classes q and v shall be a "qml" or "q" as required in mil-prf-38535. the compliance mark for device class m shall be a "c" as required in mil-prf-38535, appendix a. 3.6 certificate of compliance . for device classes q and v, a certificate of compliance shall be required from a qml-38535 listed manufacturer in order to supply to t he requirements of this draw ing (see 6.6.1 herein). for device class m, a certifica te of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in mil-hdbk-103 (see 6.6.2 herein). the certificate of compliance submitted to dscc-va prior to lis ting as an approved source of supply for this drawing shall affirm that the manufacture r's product meets, for device classes q and v, the requirement s of mil-prf-38535 and herein or for device class m, the require ments of mil-prf-38535, appendix a and herein. 3.7 certificat e of conformance . a certificate of conformanc e as required for device classes q and v in mil-prf-38535 or for device class m in mil-prf-38535, appendix a shall be provided with each lot of microcircuits delivered to this drawing. 3.8 notification of change for device class m . for device class m, notification to dscc-va of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 verification and review for device class m . for device class m, dscc, dscc's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable requir ed documentation. offshore documentation shall be made available onshore at the option of the reviewer. 3.10 microcircuit group assignment for device class m . device class m devices covered by this drawing shall be in microcircuit group number 42 (see mil-prf-38535, appendix a). 3.11 processing of eeproms : all testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.11.1 conditions of the supplied devices : devices will be supplied in cleared state (logic "1's"). no provision will be made for supplying written devices. 3.11.2 clearing of eeproms : when specified, devices shall be clear ed in accordance with the procedures and characteristics spec ified in 4.6.4. 3.11.3 writing of eeproms : when specified, devices sha ll be written in accordance with the procedures and characteristics specified in 4.6.3. 3.11.4 verification of state of eeproms : when specified, devices shall be verified as either written to the specified pattern or cleared. as a minimum, verification shall consist of performing a read of the entire array to veri fy that all bits are in the proper state. any bit that does not verify to be in the proper state shall constitute a device failure and the device shall be remove d from the lot or sample. 3.11.5 power supply sequence of eeproms : in order to reduce the probability of inadvertent writes, the following power supply sequences shall be observed: a. a logic high state shall be applied to we and/or ce at the same time or before the application of v cc . b. a logic high state shall be applied to we and/or ce at the same time or before the removal of v cc . 4. verification 4.1 sampling and inspection . for device classes q and v, sampling and inspection procedures shall be in accordance with mil-prf-38535 or as modified in the devic e manufacturer's quality m anagement (qm) plan. the modification in the qm plan shall not affect the form, fit, or functi on as described herein. for device class m, sampling and inspection procedures shall be in accordance with mil-prf-38535, appendix a.
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 6 dscc form 2234 apr 97 4.2 screening . for device classes q and v, screening shall be in accordance with mil-prf- 38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. fo r device class m, screening shall be in accordance with method 5004 of mil-std-883, and shall be conducted on all devices prio r to quality conformance inspection. 4.2.1 additional criteria for device class m . a. delete the sequence specified as initial (preburn-in) electrical par ameters through interim (postburn-in) electrical parameters of met hod 5004 and substitute lines 1 through 6 of table iia herein. b. prior to burn-in, the devices s hall be programmed (see 4.6.3 herein) with a checkerboard pattern or equivalent (manufacturers at their option may empl oy an equivalent pattern provided it is a topologically true alternating bit pattern). (see figure 4.) the pattern shall be read bef ore and after burn in. devices having bits not in the proper state after burn in shall constitute a device failure and shall be included in the percent defective allowable (pda) calculation and shall be re moved from the lot (see 4.2.3 herein). c. the test circuit shall be maintained by the manufac turer under document revision level control and shall be made available to the preparing or acquiring activity upon request. t he test circuit shall specify the inputs, out puts, biases, and power dissipation, as applicable, in accordanc e with the intent s pecified in method 1015. (1) dynamic burn-in for device class m (method 1015 of mi l-std-883, test condition d or e) using the circuit submitted ( see 4.2.1c herein). d. interim and final electrical parameters shall be as specified in table iia herein. e. an endurance test including a data ret ention bake, as specified in method 1033 of mil-std-883, prior to burn-in (e.g., may be performed at wafer sort) shall be included as part of the screening procedure, wi th the following conditions: (1) cycling may be chip, block, byte or page at equipment room ambient and shall cycle all bytes a minimum of 10,000 cycles. (2) after cycling, perform a high te mperature unbiased st orage 48 hours at +150 c minimum. the storage time may be accelerated by a higher temperat ure in accordance with the arrheni us relationship and with the apparent activation energy of 0.6 ev. the maximu m storage temperature shall not exceed +200 c for assembled devices and +300 c for unassembled devices. all devices shall be pr ogrammed with a charge oppos ite the stat e that the cell would read in its equilibrium state (e.g . worst case pattern, see 3.12.3 herein). (3) read the data retention pattern and test using subgroups 1, 7, and 9 (at t he manufacturer's option high temperature equivalent subgroups 2, 8a, and 10 or low temperature equivalent subgroups 3, 8b, and 11 may be used in lieu of subgroups 1, 7, and 9) after cycling and bak e, but prior to burn-in. devices havi ng bits not in the proper state after storage shall constitute a device failure. g. after the completion of all screening, the devices shall be eras ed and verified prior to delivery. 4.2.2 additional criteria for device classes q and v . a. the burn-in test duration, test condi tion and test temperature, or approved alte rnatives shall be as specified in the device manufacturer's qm plan in accordance with mil-prf- 38535. the burn-in test circuit shall be maintained under document revision level control of the device manufacturer's technology review board (trb) in accordance with mil-prf-38535 and shall be made available to the acquiring or preparing activity upon request. the test circuit shall specify the inputs, output s, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of mil-std-883. b. interim and final electrical test parameter s shall be as specified in table iia herein. c. additional screening for device class v beyond the require ments of device class q shall be as specified in mil-prf-38535, appendix b.
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 7 dscc form 2234 apr 97 table i. electrical performance characteristics . limits test symbol conditions -55 c t c +125 c v ss = 0 v; 4.5 v v cc 5.5 v unless otherwise specified group a subgroups device type min max unit high level input current i ih v cc = 5.5 v, v in = 5.5 v 1,2,3 (3010) all -5 5 a low level input current i il v cc = 5.5 v, v in = 0.1 v 1,2,3 (3009) all -5 5 a v cc = 5.5 v, v o = 5.5 v high impedance output leakage current 1 / i ozh v ih oe v cc 1,2,3 (3021) all -10 10 a v cc = 5.5 v, v o = 0.0 v i ozl v ih oe v cc 1,2,3 (3020) -10 10 i oh = -400 a, v cc = 4.5 v output high voltage v oh v ih = 2.0 v, v il = 0.8 v 1,2,3 (3006) all 2.4 v i ol = 2.1 ma, v cc = 4.5 v output low voltage v ol v ih = 2.0 v, v il = 0.8 v 1,2,3 (3007) all 0.4 v input high voltage 2 / v ih v cc = 5.5 v 1,2,3 (3008) all 2.0 6.0 v input low voltage 2 / v il v cc = 4.5 v 1,2,3 (3008) all -0.5 0.8 v oe high voltage v h 1,2,3 all 15 16 v v cc = 5.5 v, we = v ih , ce = oe = v il operating supply current i cc1 f = 1/t avav min 1,2,3 (3005) all 50 ma v cc = 5.5 v, ce = v ih , all i/o's = open, standby supply current ttl i cc2 oe = v il , f = 0 hz 1,2,3 (3005) all 3 ma v cc = 5.5 v, ce = v cc -0.3 v inputs = v ih , i/o's = open, standby supply current cmos i cc3 oe = v il , f = 0 hz 1,2,3 (3005) 500 a see footnotes at end of table.
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 8 dscc form 2234 apr 97 table i. electrical performance characteristics - continued. limits test symbol conditions -55 c t c +125 c v ss = 0 v; 4.5 v v cc 5.5 v unless otherwise specified group a subgroups device type min max unit v in = 0 v, f = 1.0 mhz, input capacitance 3 / 4 / c in t c = +25 c, see 4.4.1d 4 (3012) all 10.0 pf v out = 0 v, f = 1.0 mhz output capacitance 3 / 4 / c out t c = +25 c, see 4.4.1d 4 (3012) all 10.0 pf functional tests see 4.4.1b 7, 8a, 8b (3014) all 01-02 09-10 250 03,04, 11,12 200 05,06, 13,14 150 read cycle time t avav see figures 5, 6, and 7 as applicable. 5 / 9, 10, 11 (3003) 07,08, 15,16 120 ns 01,02, 09,10 250 03,04, 11,12 200 05,06, 13,14 150 address access time t avqv 9, 10, 11 (3003) 11,12, 15,16 120 ns 01-02 09,10 250 03,04, 11,12 200 05,06, 13,14 150 ce access time t elqv 9, 10, 11 (3003) 07,08, 15,16 120 ns oe access time t olqv 9, 10, 11 (3003) all 50 ns ce to output in low z 4 / t elqx see figures 5, 6, and 7 as applicable 9, 10, 11 (3003) all 0 ns chip disable to output in high z 4 / t ehqz 9, 10, 11 (3003) all 50 ns see footnotes at end of table.
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 9 dscc form 2234 apr 97 table i. electrical performance characteristics - continued. limits test symbol conditions -55 c t c +125 c v ss = 0 v; 4.5 v v cc 5.5 v unless otherwise specified group a subgroups device type min max unit oe to output in low z 4 / t olqx see figures 5, 6, and 7 as applicable. 9, 10, 11 (3003) all 0 ns output disable to output in high z 4 / t ohqz 9, 10, 11 (3003) all 50 ns output hold from address change t axqx see figures 5, 6, and 7 as applicable. 5 / 9, 10, 11 (3003) all 0 ns 01,03, 05,07, 09,11, 13,15 10 write cycle time t whwl1 t ehel1 9, 10, 11 (3003) 02,04, 06,08, 10,12, 14,16 5 ns address setup time t avwl t avel 9, 10, 11 (3003) all 0 ns address hold time t wlax t elax 9, 10, 11 (3003) all 50 ns write setup time t elwl t wlel 9, 10, 11 (3003) all 0 ns write hold time t wheh t ehwh 9, 10, 11 (3003) all 0 ns oe setup time t ohwl t ohel 9, 10, 11 (3003) all 10 ns oe hold time t whol t ehol 9, 10, 11 (3003) all 10 ns write pulse width (page or byte write) t wlwh t eleh 9, 10, 11 (3003) all .100 s see footnotes at end of table.
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 10 dscc form 2234 apr 97 table i. electrical performance characteristics - continued. limits test symbol conditions -55 c t c +125 c v ss = 0 v; 4.5 v v cc 5.5 v unless otherwise specified group a subgroups device type min max unit data setup time t dvwh t dveh see figures 5, 6, and 7 as applicable. 5 / 9, 10, 11 (3003) all 50 ns data hold time t whdx t ehdx 9, 10, 11 (3003) all 10 ns byte load cycle t whwl2 9, 10, 11 (3003) all .20 100 s 01,02, 09,10 250 03,04, 11,12 200 05,06, 13,14 150 last byte loaded to data polling t whel t ehel 9, 10, 11 (3003) 07,08, 15,16 120 ns ce setup time t elwl 9, 10, 11 (3003) all 5 s oe setup time (chip erase) t ovhwl 9, 10, 11 (3003) all 5 s we pulse width (chip clear) t wlwh2 9, 10, 11 (3003) all 10 ms ce hold time (chip erase) t wheh 9, 10, 11 (3003) all 5 s oe hold time t whoh 9, 10, 11 (3003) all 5 s high voltage (chip erase) v h 9, 10, 11 (3003) all 12 13 v clear recovery t olel see figures 5, 6, and 7 as applicable. 9, 10, 11 (3003) all 50 ms data setup time 6/ t dhwl 9, 10, 11 (3003) all 1 s data hold time during chip erase cycle 6 / t whdx 9, 10, 11 (3003) all 1 s see footnotes on next page.
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 11 dscc form 2234 apr 97 table i. electrical performance characteristics - footnotes. 1 / connect all address inputs and oe to v ih and measure i ozl and i ozh with the output under test connected to v out . terminal conditions for the output leakage current test shall be as follows: a. v ih = 2.0 v: v il = 0.8 v. b. for i ozl : select an appropriate address to acquire a logic "1" on the designated output. apply v ih to ce . measure the leak age current while applying the specified voltage. c. for i ozh : select an appropriate address to acquire a logic "0" on the designated output. apply v ih to ce . measure the leak age current while applying the specified voltage. 2 / a functional test shall verify the dc input and out put levels and applicable patterns as appropriate, all input and i/o pins shall be tested. terminal conditions are as follows: a. inputs: h = 2. 0 v: l = 0.8 v. b. outputs: h = 2.4 v mi nimum and l = 0.4 v maximum. c. the functional tests shall be performed with v cc = 4.5 and v cc = 5.5 v. 3 / all pins not being tested are to be open. 4 / tested initially and after any design or process changes which may affect that param eter, and therefore shall be guaranteed to the limits specified in table ia. 5 / tested by application of spec ified timing signals and conditions. equivalent a.c. test conditions: output load: see figure 8. input rise and fall times 10 ns. input pulse levels: 0.4 v and 2.4 v. timing measurement reference levels: inputs: 1.5 v. outputs: 1.5 v. 6 / this parameter not applicable for internal timer controlled devices. 4.3 qualification inspection . 4.3.1 qualificat ion inspection for device classes q and v . qualification inspection for device classes q and v shall be in accordance with mil-prf-38535. inspections to be performed shall be those specified in mil-prf-38535 and herein for groups a, b, c, d, and e inspecti ons (see 4.4.1 through 4.4.5). 4.3.2 electrostatic disc harge sensitivity inspection . electrostatic discharge sensitivity (esds) testing shall be performed in accordance with mil-std-883, method 3015. esds testing shall be measured only for in itial qualification and after process or design changes which may affect esds classification. 4.4 conformance inspection . technology conformance inspection for classes q and v shall be in accordance with mil-prf-38535 including groups a, b, c, d, and e inspections and as specified herei n except where option 2 of mil-prf- 38535 permits in-line control testing. qua lity conformance inspection for device cla ss m shall be in accordance with mil-prf- 38535, appendix a and as specified herein. in spections to be performed for device cla ss m shall be those specified in method 5005 of mil-std-883 and herein for gr oups a, b, c, d, and e inspec tions (see 4.4.1 through 4.4.5).
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 12 dscc form 2234 apr 97 dimensions letter inches millimeters a b b1 c d e e1 e l l1 q s s1 .232 max .014/.023 .033/.065 .008/.015 1.690 max .570/.610 .590/.620 .100 bsc .125/.200 .150 min .015/.060 .100 max .005 min 5.89 0.36/0.58 0.84/1.66 0.20/0.38 42.93 14.48/15.49 14.99/15.76 2.54 3.18/5.08 3.81 0.38/1.51 2.54 0.13 note: configurations a and c of mil-std-1835 may be used. figure 1. case outline .
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 13 dscc form 2234 apr 97 case z figure 1. case outline - continued.
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 14 dscc form 2234 apr 97 case z - continued variations (all dimensions shown in inches) symbol min max notes a b b1 c c1 d e e1 e2 e3 .090 .015 .015 .004 .004 .430 .330 .030 .120 .020 .019 .007 .006 .830 .488 .498 .498 4 8 e .050 bsc h k .008 1.228 .015 2, 5 k1 .025 ref 2, 5 l q s1 .270 .026 .370 .045 .045 3 n 32 6 inches mm inches mm inches mm .004 0.10 .020 0.51 .270 6.86 .005 0.13 .025 0.64 .350 8.89 .006 0.15 .026 0.66 .370 9.40 .007 0.18 .030 0.76 .472 11.99 .008 0.20 .045 1.14 .488 12.40 .015 0.38 .050 1.27 .498 12.65 .019 0.48 .120 3.05 1.228 31.19 notes: 1. all dimensions and tolerances conform to ansi y14.5m-1982. 2. index area: an identificat ion mark shall be located adjacent to pin 1 wi thin the shaded area shown. alternatively, a tab (dim k) may be used as shown. 3. dimension q shall be measur ed from the point on the lead located opposite the braze pad. 4. this dimension includes lid thickness. 5. optional, see note 2. if pin 1 ident ification is used instead of this tab, the minimum dimension does not apply. 6. (n) indicates number of leads. 7. uses a metal lid. 8. includes braze fillet. 9. metric equivalents are given for general information only. figure 1. case outline - continued.
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 15 dscc form 2234 apr 97 case u figure 1. case outline - continued.
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 16 dscc form 2234 apr 97 device types 01-08 09-16 case outlines x, y, and z u y terminal number terminal symbol 1 2 3 4 5 nc nc a 15 a 12 a 7 nc nc nc nc a 15 a 15 a 14 a 12 a 7 a 6 6 7 8 9 10 a 6 a 5 a 4 a 3 a 2 a 12 a 7 a 6 a 5 a 4 a 5 a 4 a 3 a 2 a 1 11 12 13 14 15 a 1 a 0 i/o 0 i/o 1 i/o 2 a 3 a 2 a 1 a 0 i/o 0 a 0 nc i/o 0 i/o 1 i/o 2 16 17 18 19 20 v ss i/o 3 i/o 4 i/o 5 i/o 6 i/o 1 i/o 2 v ss i/o 3 i/o 4 v ss nc i/o 3 i/o 4 i/o 5 21 i/o 7 i/o 5 i/o 6 22 ce i/o 6 i/o 7 23 a 10 i/o 7 ce 24 oe ce a 10 25 a 11 a 10 oe 26 27 28 29 30 a 9 a 8 a 13 a 14 nc oe a 11 a 9 a 8 a 13 nc a 11 a 9 a 8 a 13 31 we a 14 we 32 v cc nc v cc 33 34 -- -- nc nc -- -- 35 -- we -- 36 -- v cc -- nc = no connection figure 2. terminal connections .
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 17 dscc form 2234 apr 97 v ih = high logic, "1" state, v il = low logic, "0" state. x = logic "don't care" state, high z = high impedance state. v h = chip clear voltage, d out = data out, and d in = data in. figure 3. truth table . mode ce oe we i/o read v il v il v ih d out write v il v ih v il d in standby v ih x x high z write inhibit x x v ih d out or high z write inhibit v ih x x high z write inhibit x v il x d out or high z write inhibit v il v il v il no operation software chip clear v il v ih v il d in software write protect v il v ih v il d in high voltage chip clear v il v h v il v ih
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 18 dscc form 2234 apr 97 notes: 1. all address numbers shown in decimal. 2. each column/row address lo cation corresponds to 1 byte. 3. all data numbers shown in hexadecimal. aa = 10101010 55 = 01010101 4. manufacturers at their option may employ an equivalent pattern provided it is a topologically true alternating bit pattern. figure 4. data pattern . 0 1 2 3 4 5 6 225 226 509 510 511 r 0 aa aa aa aa aa aa aa aa aa aa aa aa aa aa 0 1 55 55 55 55 55 55 55 55 55 55 55 55 55 55 w 2 aa aa aa aa aa aa aa aa aa aa aa aa aa aa 3 55 55 55 55 55 55 55 55 55 55 55 55 55 55 a d d r 125 aa aa aa aa aa aa aa aa aa aa aa aa aa aa e 126 55 55 55 55 55 55 55 55 55 55 55 55 55 55 s 127 aa aa aa aa aa aa aa aa aa aa aa aa aa aa s 128 55 55 55 55 55 55 55 55 55 55 55 55 55 55
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 19 dscc form 2234 apr 97 figure 5. read mode waveforms .
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 20 dscc form 2234 apr 97 we controlled byte write waveforms (all device types) figure 6. waveforms .
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 21 dscc form 2234 apr 97 ce controlled byte write waveforms (all device types) figure 6. waveforms - continued.
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 22 dscc form 2234 apr 97 page mode write cycle waveforms (all device types) figure 6. waveforms - continued.
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 23 dscc form 2234 apr 97 (all device types) figure 7. chip erase mode waveforms .
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 24 dscc form 2234 apr 97 notes: 1. v oh and v ol will be adjusted to meet load conditions of table i. 2. use this circuit or equivalent circuit. figure 8. switching load circuit
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 25 dscc form 2234 apr 97 notes: 1. software chip clear timings are referenced to we and ce inputs, whichever is last to go low, and the we or ce inputs, whichever is first to go high. 2. the command sequence must conf orm to the page write timing. figure 9. software chip clear and software write protect algorithm (all device types) . write data aa to address 5555 write data 55 to address 2aaa write data 80 to address 5555 write data aa to address 5555 write data 55 to address 2aaa write data 10 to address 5555
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 26 dscc form 2234 apr 97 notes: 1. reset software data protection timings are referenced to the we or ce inputs, whichever is last to go low, and the we or ce inputs, whichever is first to go high. 2. a minimum of one valid byte write must follo w the first three bytes of the command sequence. 3. the command sequence and s ubsequent data must confo rm to page write timing. figure 10a. set software write protec t and software protected write algorithm . write data aa to address 5555 write data 55 to address 2aaa write data ao to address 5555 set swp byte/page load enabled write data xx to any address write last byte to last address after t wc re-enters data protected state
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 27 dscc form 2234 apr 97 notes: 1. reset software data protection timings are referenced to the we or ce inputs, whichever is last to go low, and the we or ce inputs, whichever is first to go high. 2. the command sequence must conf orm to the page write timing. figure 10b. reset software write protect algorithm . write data aa to address 5555 write data 55 to address 2aaa write data 80 to address 5555 write data aa to address 5555 write data 55 to address 2aaa swp reset write data 20 to address 5555
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 28 dscc form 2234 apr 97 table iia. electrical test requirements . 1 / 2 / 3 / 4 / 5 / 6 / 1 / blank spaces indicate tests are not applicable. 2 / any or all subgroups may be comb ined when using high-speed testers. 3 / subgroups 7, 8a, and 8b functional te sts shall verify the truth table. 4 / * indicates pda applies to subgroup 1 and 7. 5 / ** see 4.4.1d. 6 / ? indicates delta limit (see table iib) shall be required wher e specified, and the delta va lues shall be computed with reference to the previous electr ical parameters (see table iib). 7 / see table iii. 8 / delta limits required for initial qualif ication and after any design or process change. subgroups (in accordance with mil-std-883, method 5005, table i) subgroups (in accordance with mil-prf-38535, method 5005, table iii) line no. test requirements device class m device class q device class v 1 interim electrical parameters (see 4.2) 1,7,9 or 2,8a,10 1,7,9 or 1,2,8a,10 2 static burn-in i & ii (method 1015) not required not required required 3 same as line 1 1*,7* ? 4 dynamic burn-in (method 1015) required required required 5 same as line 1 1*,7* ? 6 final electrical parameters 1*,2,3,7*, 8a,8b,9,10, 11 1*,2,3,7*, 8a,8b,9,10, 11 1*,2,3,7*, 8a,8b,9,10, 11 7 group a test requirements 7 / 1,2,3,4**,7, 8a,8b,9,10, 11 1,2,3,4**,7, 8a,8b,9,10, 11 1,2,3,4**,7, 8a,8b,9,10, 11 8 group c end-point electrical parameters 2,3,7, 8a,8b 1,2,3,7, 8a,8b,9,10,11 8 / ? 9 group d end-point electrical parameters 2,3,7, 8a,8b 2,3,7, 8a,8b 2,3,7, 8a,8b 10 group e end-point electrical parameters 1,7,9 1,7,9 1,7,9
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 29 dscc form 2234 apr 97 table iib. delta limits at +25 c . device types test 1 / all i cc3 standby 10% of specified value in table i i ih , i il 10% of specified value in table i i ohz , i olz 10% of specified value in table i 1 / the above parameters shall be recorded before and after the required burn-in and life tests to determine the delta ? . table iii. input/output pulse levels for table i, subgroups 7, 8a, 8b, 9, 10, and 11 . symbol terminals a b device type units v cc v cc 4.5 5.5 all v v ih logic inputs address and control pins 2.4 2.4 all v v il logic inputs address and control pins 0.4 0.4 all v v oh logic output compare level 2.0 2.0 all v v ol logic output compare level 0.8 0.8 all v t avqv address 250 200 150 120 250 200 150 120 01,02,09,10 03,04,11,12 05,06,13,14 07,08,15,16 ns ns ns ns t elqv chip enable 250 200 150 120 250 200 150 120 01,02,09,10 03,04,11,12 05,06,13,14 07,08,15,16 ns ns ns ns t olqv output enable 50.0 50.0 all ns t axqx i/o 0 ? i/o 7 0.0 0.0 all ns note: 1. for v oh and v ol , the logic output compare levels shall be 1.5 v for subgroups 9, 10, and 11 only.
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 30 dscc form 2234 apr 97 4.4.1 group a inspection . a. tests shall be as specif ied in table iia herein. b. for device class m, subgroups 7, 8a, and 8b tests shall be su fficient to verify the truth table. for device classes q and v subgroups 7, 8a, and 8b shall include verifying the functiona lity of the device. c. o/v (latch-up) tests shall be meas ured only for initial qualification and after any design or process changes which may affect the performance of the device. for device class m, procedures and ci rcuits shall be maintained under document revision level control by the manufactu rer and shall be made available to the preparing activity or acquiring activity upon request. for device classes q and v, the procedures and circuits shall be under t he control of the device manufacturer's trb in accordance with mil-prf-38535 and s hall be made available to the preparing activity or acquiring activity upon request. testing shall be on all pins, on fi ve devices with zero failures. latch-up test shall be considered destructive. information contained in je dec standard eia/jesd 78 ma y be used for reference. d. subgroup 4 (c in and c out measurements) shall be measured only for in itial qualification and after any process or design changes which may affect input or output capacitance. capacitance shall be meas ured between the designated terminal and gnd at a frequency of 1 mhz. sample size is fifteen devices with no failu res, and all input and output terminals tested. e. all devices selected for testing sha ll be programmed with a checkerboard pattern or equivalent. after completion of all testing, the devices shall be cl eared and verified, (except device submi tted for groups b, c, and d testing). 4.4.2 group c inspection . the group c inspection end-point electrical paramet ers shall be as specified in table iia herein. delta limits shall apply only to subgroup 1 of group c inspection and shall consist of tests specified in table iib herein. 4.4.2.1 additional criteria for device class m . a. steady-state life test c onditions, method 1005 of mil-std-883: (1) the devices selected for testing shall be programmed with a checkerboard pattern. after completion of all testing, the devices shall be cleared and verified (except devices submitted for group d testing). (2) test condition d or e. the test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. the test circuit shall specify the inputs, output s, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of mil-std-883. (3) t a = +125 c, minimum. (4) test duration: 1,000 hour s, except as permitted by method 1005 of mil-std-883. b. an endurance test, as specified in method 1033 of mil-std-883, shall be added to group c, subgroup 1 inspection prior to performing the steady-state life test (see 4.4.2.1a) and ex tended data retention (see 4. 4.2.1b). cycling may be block, byte, or page from devices passing group a after the comp letion of the requirements of 4.2 herein. initially two groups of devices shall be formed, cell 1 and ce ll 2. the following conditions shall be met: (1) cell 1 shall be cycled at -55 c and cell 2 shall be cycled at +125 c for a minimum of 10,000 cycles for device types. (2) perform group a, subgroups 1, 7, and 9 after cycling. form new cells (cell 3 and cell 4) for steady-state life and extended data retention. cell 3 for st eady-state life test consists of one- half of the devices from cell 1 and one- half of the devices from cell 2. ce ll 4 for extended data retenti on consists of the remaining devices from cell 1 and cell 2. (3) extended data retention test s hall consist of the following: a. all devices shall be programmed wi th a charge on all memory cells in each device, such that loss of charge (e.g., leakage in the cell) can be detected (e.g., worst case pattern). b. unbiased bake for 1,000 hours (minimum) at +150 c (minimum). the unbiased bake time may be accelerated by using higher temperature in accor dance with the arrhenius relationship and with the apparent activation of 0.6 ev. the maximu m bake temperature shall not exceed +200 c for packaged devices or +300 c for unassembled devices.
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 31 dscc form 2234 apr 97 c. read the pattern after bake and perform end-point electr ical tests in accordance with table iia herein for group c. (4) the sample plans for cell 1, cell 2, cell 3, and cell 4 shall individually be the same as for group c, subgroup 1, as specified in method 5005 of mi l-std-883, and shall individually pa ss the specified sample plan. c. after the completion of all te sting, the devices shall be clear ed and verified prior to delivery. 4.4.3.2 additional criteria for device classes q and v . the steady-state life test duration, test condition and test temperature, or approved alternatives shall be as spec ified in the device manufacturer's qm pl an in accordance with mil-prf-38535. the steady-state life test circuit shall be ma intained under document revision level contro l by the device manufacturer's trb in accordance with mil-prf-38535 and shall be made available to the acquiring or preparing activity upon request. the test circui t shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in met hod 1005 of mil-std-883. after the completi on of all testing, the devices shall be erased and verified prior to delivery. 4.4.4 group d inspection . the group d inspection end-point electrical paramet ers shall be as specified in table iia herein. the devices selected for testing shall be programmed with a c heckerboard pattern (see figure 9). after completion of all testing, the devices s hall be erased and verified. 4.4.5 group e inspection . group e inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. end-point electrical par ameters shall be as specif ied in table iia herein. b. for device classes q and v, the devices or test vehicle shall be subjected to radi ation hardness assured tests as specified in mil-prf-38535 for the rha level being te sted. for device class m, the devices shall be subjected to radiation hardness assured tests as specified in mil-prf-38535, appendix a for the rha level being tested. all device classes must meet the postirradiation end- point electrical parameter limit s as defined in table i at t a = +25 c 5 c, after exposure, to the subgroups specified in table iia herein. 4.5 delta measurements for device classes q and v . delta measurements, as specif ied in table iia, shall be made and recorded before and after the required burn-in screens and steady-state life tests to det ermine delta compliance. the electric al parameters to be measured, with associat ed delta limits are listed in table iib. 4.6 methods of inspection . methods of inspection shall be as specif ied in the appropriate tables and as follows. 4.6.1 voltages and current . all voltages given are referenced to the mi crocircuit ground terminal. currents given are conventional and positive when flowi ng into the referenced terminal. 4.6.2 life test, burn-in, cool down and electrical test procedure . when devices are measured at +25 c following application of the steady state life or burn- in test condition, all devices shall be cooled to +35 c or within +10 c of the power stable condition prior to removal of bias voltages/signals. any elec trical tests required shall first be performed at -55 c or +25 c prior to any required tests at +125 c. 4.6.3 writing procedure . the waveforms and timing relationships shown on figure 6 and the conditions specified in table ia shall be adhered to. initially and after each chip clear (see 4.6.4), all bits are in t he high state (output at v oh ). 4.6.3.1 byte write operation . information is introduced by selectively writing "l" (logic "0" level) or "h" (logic "1" level) into the desired bit. a written "l" can be changed to an "h" by writ ing an "h". no clearing is necessary (see 4.6.4). 4.6.3.2 page write operation . the page write operation can be initiat ed during any write operation. following the initial byte write cycle, the hos t can write an additional one to 127 bytes in the same manner as the first byte was written. each successive byte load cycle, started by the we ( ce ) high to low transition, must begin within 150 s of the falling edge of the preceding we ( ce ) high to low transition, [twlwh1+twhwl2] or [teleh1+tehel2]. if a subsequent we high to low transition is not detected within 150 s, the internal automatic write cycle will commence. the successive writes need not be sequentia l; however, the page address (a7 through a16) for each write during a page write oper ation shall be the same. 4.6.3.3 data polling operation . during the internal writing cycle after a by te or page write operation, an attempt to read the last byte written will produce the comple ment of that data on all i/o or i/07 (i .e., write data - 0xxx xxxx and read data - 1xx x xxx). once the writing cycle has completed, all i/0 or i/o7 will reflect true data (i.e. write dat a - 0xxx xxx, read data - 0xxx xxx) . 4.6.3.4 toggle bit . toggle bit determines the end of the internal write cycl e. while the internal write cycle is in progress i/0 6 toggles from 1 to 0 and 0 to 1 on sequential polling reads. when the internal write cycle is complete, the toggling stops and the device is ready for additional read/write operations.
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 32 dscc form 2234 apr 97 4.6.4 clearing procedure . the waveforms and timing relationship shown on fi gures 5, 6, 7, and 8 and the conditions specified in table ia shall be adhered to. initially and after each ch ip clear, all bits are in the high state (output at v oh ). 4.6.4.1 byte clearing . a byte is cleared by simultaneously writing an "h " state into each bit at the selected address (see 4.6.3). this can be done by a byte write cy cle or a page mode write cycle (see figure 6). 4.6.4.2 software chip clear . software chip clear is performed by executing a se ries of instructions to the device (see figure 9). at the end of the step sequence, the device begins and completes chip clear internally. the waveforms and timing relationship s shown on figures 6 and 7, and the test conditi ons and limits specified in table ia apply. 4.6.4.3 high voltage chip clear . the device is cleared by setting the oe (output enable) pin to v h (see figure 7) while all other inputs are set in the normal byte eras e mode (see 4.6.4.2). after chip clear, all bits are in the "h" state. (applies t o all device types.) 4.6.5 read mode operation . the device is in the read mode whenever the ce and oe pins are at v il . the waveforms and timing relationships shown on figure 5 and the test condi tions and limits specified in table i shall be applied. 4.6.6 extended page load . the write cycle must be "stretched" by maintaining we low, assuming a write enable-controlled cycle, and leavi ng all other control inputs ( ce , oe ) in the proper page load cycle state. since the page load timer is reset on the falling edge of we , keeping this signal low will inhibit the page timer. when we returns high, the input data is latc hed and the page load cycle timer begins in ce controlled write. the same is true, with ce holding the timer reset instead of we . 4.6.7 software data protection . device types 01 through 15 software data pr otection offers a method of preventing inadvertent writes. the instruction, waveforms, and timing relationships shown on figures 5, 6, 10a, and figure 10b, and the conditions specified in table ia shall apply. 4.6.7.1 set software protection . device types 01 through 15 are placed in protect ed state by writing a seri es of instructions (see figure 10a) to the device. once pr otected, writing to the dev ice may only be preformed by executing the same sequence of instructions appended with either a by te write operation or page wr ite operation. the waveforms and timing relationship shown on figure 6 and the test conditions and limits specified in table ia apply. 4.6.7.2 reset software data protection . device types 01 through 15 protection feat ure is reset by writing a series of instructions (see figure 10b) to the device. the waveforms and timing relationships shown on figure 6 and the test conditions and limits specified in table ia apply. 5. packaging 5.1 packaging requirements . the requirements for packaging shall be in accordance with mil-prf-38535 for device classes q and v or mil-prf-38535, appendix a for device class m. 6. notes 6.1 intended use . microcircuits conforming to this drawing are int ended for use for government microcircuit applications (original equipment), design applic ations, and logistics purposes. 6.1.1 replaceability . microcircuits covered by this drawing will repl ace the same generic device covered by a contractor prepared specificati on or drawing. 6.1.2 substitutability . device class q devices will replace device class m devices. 6.2 configurati on control of smd's . all proposed changes to existing smd's will be coordinated with the users of record for the individual documents. this c oordination will be accomplished using dd form 1692, engineering change proposal. 6.3 record of users . military and industrial users should inform defens e supply center columbus (dscc) when a system application requires configuration control and which smd's are applicabl e to that system. dscc will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. users of drawings covering microelect ronic devices (fsc 5962) should contac t dscc-va, telephone (614) 692-0544. 6.4 comments . comments on this drawing should be directed to dscc-va , columbus, ohio 43218-3990, or telephone (614) 692-0547.
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 33 dscc form 2234 apr 97 6.5 abbreviations, symbols, and definitions . the abbreviations, symbols, and defin itions used herein are defined in mil-prf-38535 and mil-hdbk-1331 and herein: c in and c out .......................... input and bidirectional output, te rminal-to-gnd capacitance. gnd....................................... gr ound zero voltage potential. i cc .......................................... s upply current. i il ............................................ input current low. i ih ........................................... input current high. t c ........................................... case temperature. t a ........................................... ambient te mperature. v cc ......................................... positi ve supply voltage. v h ........................................... output enable and write enable voltage during chip erase. o/v......................................... latch- up over-voltage 6.5.1 timing limits . the table of timing values shows either a mini mum or a maximum limit for each parameter. input requirements are specified from t he external system point of view. thus, addre ss setup time is shown as a minimum since the system must supply at least that much ti me (even though most devices do not require it). on the other hand, responses from the memory are specified from the device point of view. thus, the access time is shown as a maximum since the device never provides data later than that time. 6.5.2 timing parameter abbreviations . all timing abbreviations use lower case characters with upper case character subscripts. the initial character is always "t" and is followed by four descriptors. these characters specify two signal poin ts arranged in a "from-to" sequence t hat define a timing interval. the two descrip tors for each signal specify the signal name an d the signal transition. thus the format is: t x x x x signal name from which interval is defined transition direction for first signal signal name to which interval is defined transition direction for second signal a. signal definitions: a = address d = data in q = data out w = write enable e = chip enable o = output enable b. transition definitions: h = transition to high l = transition to low v = transition to valid x = transition to invalid or don't care z = transition to off (high impedance)
standard microcircuit drawing size a 5962-90869 defense supply center columbus columbus, ohio 43218-3990 revision level c sheet 34 dscc form 2234 apr 97 6.5.3 waveforms . waveform symbol input output must be valid will be valid change from h to l will change from h to l change from l to h will change from l to h don't care any change permitted changing state unknown high impedance 6.6 sources of supply . 6.6.1 sources of supply for device classes q and v . sources of supply for device classes q and v are listed in qml-38535. the vendors listed in qml-38535 have submi tted a certificate of co mpliance (see 3.6 herein) to dscc-va and have agreed to this drawing. 6.6.2 approved sources of supply for device class m . approved sources of supply for cl ass m are listed in mil-hdbk-103. the vendors listed in mil-hdbk-103 have agr eed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by dscc-va.
standard microcircuit drawing bulletin date: 07-04-13 approved sources of supply for smd 5962-90869 are listed below for immediate acquisition information only and shall be added to mil-hdbk-103 and qml-38535 during the next re vision. mil-hdbk-103 and qml-38535 will be revised to include the addition or deletion of s ources. the vendors listed below have agr eed to this drawing and a certificate of compliance has been submitted to and accepted by dscc-va. this informati on bulletin is superseded by the next dated revision of mil-hdbk-103 and qml- 38535. dscc maintains an online databas e of all current sources of supply at http://www.d scc.dla.mil/programs/smcr/ . standard microcircuit drawing pin 1 / vendor cage number vendor similar pin 2 / 5962-9086901mxa 34371 x28c512dmb-25 5962-9086901mya 34371 x28c512emb-25 5962-9086901mzc 3 / x28c512fmb-25 5962-9086901muc 3 / x28c512kmb-25 5962-9086902mxa 3 / x28c512dmb-25 5962-9086902mya 34371 x28c512emb-25 5962-9086902mzc 3 / x28c512fmb-25 5962-9086902muc 3 / x28c512kmb-25 5962-9086903mxa 34371 x28c512dmb-20 5962-9086903mya 3 / x28c512emb-20 5962-9086903mzc 3 / x28c512fmb-20 5962-9086903muc 3 / x28c512kmb-20 5962-9086904mxa 3 / x28c512dmb-20 5962-9086904mya 3 / x28c512emb-20 5962-9086904mzc 3 / x28c512fmb-20 5962-9086904muc 3 / x28c512kmb-20 5962-9086905mxa 34371 x28c512dmb-15 5962-9086905mya 3 / x28c512emb-15 5962-9086905mzc 3 / x28c512fmb-15 5962-9086905muc 3 / x28c512kmb-15 5962-9086906mxa 34371 x28c512dmb-15 5962-9086906mya 34371 x28c512emb-15 5962-9086906mzc 3 / x28c512fmb-15 5962-9086906muc 3 / x28c512kmb-15 see footnotes at end of list. page 1 of 2
standard microcircuit drawing bulletin ? continued. standardized military drawing pin vendor cage number vendor similar pin 1 / 5962-9086907mxa 34371 x28c512dmb-12 5962-9086907mya 3 / x28c512emb-12 5962-9086907mzc 3 / x28c512fmb-12 5962-9086907muc 3 / x28c512kmb-12 5962-9086908mxa 3 / x28c512dmb-12 5962-9086908mya 34371 x28c512emb-12 5962-9086908mzc 3 / x28c512fmb-12 5962-9086908muc 3 / x28c512kmb-12 5962-9086909mya 3 / x28c513emb-25 5962-9086910mya 3 / x28c513emb-25 5962-9086911mya 3 / x28c513emb-20 5962-9086912mya 3 / x28c513emb-20 5962-9086913mya 3 / x28c513emb-15 5962-9086914mya 3 / x28c513emb-15 5962-9086915mya 3 / x28c513emb-12 5962-9086916mya 3 / x28c513emb-12 1 / the lead finish shown for each pin representing a hermetic package is the most readily available from the manufacturer listed for that part. if the desired lead finish is not lis ted contact the vendor to determine its availability. 2 / caution . do not use this number for item acquisition. items acquired to this number may not satisfy the perfo rmance requirements of this drawing. 3 / not available from an approved source of supply. vendor cage vendor name number and address 34371 intersil corporation 1001 murphy ranch road milpitas, ca 95035- 5680 page 2 of 2 the information contained herein is di sseminated for convenience only and the government assumes no liability whats oever for any inaccuracies in the information bulletin.

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